Title:
OPERATIONAL AMPLIFIER
Document Type and Number:
Japanese Patent JP2853114
Kind Code:
B2
Abstract:
PURPOSE: To reduce energy consumption by performing the cascade connection of C-MOS and feeding the output of the C-MOS in the final step back to the gate of the C-MOS in the first step.
CONSTITUTION: This operational amplifier is constituted by the cascade connection of C-MOS m1-m3, input voltages V1, and V2 (subtracting elements) are inputted through capacitors C1 and C2 to the gate of the C-MOS m1 in the first step, and the added result of the respective input voltages V1 and V2 is turned to an input voltage. In this case, the input voltage V2 is connected through an inverter m1 composed of the C-MOS to the capacitor C2 so that the respective input voltages V1 and V2 can be correspondent to conventional voltages +V1 and -V2. Then, the output of the C-MOS m1 is inputted to the gate of the C-MOS m2, and the output of the C-MOS m2 is inputted to the gate of the C-MOS m3. Thus, output sensitivity (the rising sharpness of an output) is improved.
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Inventors:
UIWATSUTO UONWARAUIPATSUTO
KOTOBUKI KOKURYO
YO IKO
TAKATORI SUNAO
YAMAMOTO MAKOTO
KOTOBUKI KOKURYO
YO IKO
TAKATORI SUNAO
YAMAMOTO MAKOTO
Application Number:
JP21971292A
Publication Date:
February 03, 1999
Filing Date:
July 27, 1992
Export Citation:
Assignee:
YOZAN KK
SHAAPU KK
SHAAPU KK
International Classes:
G06G7/12; H03F3/21; H03F3/345; (IPC1-7): G06G7/12; H03F3/345
Attorney, Agent or Firm:
Yamamoto Makoto