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Title:
OUTPUT BUFFER CIRCUIT AND ITS DRIVING METHOD
Document Type and Number:
Japanese Patent JPH01286625
Kind Code:
A
Abstract:

PURPOSE: To decrease the energy consumption of an output buffer by D/A- converting a current with a lamp voltage generating circuit and a pulse width modulation, and switching the constant current source of an output buffer to the one for the large current and to the one for the small current with the use of the signal of the pulse width modulation.

CONSTITUTION: When a reference voltage is generated by a lamp voltage generating circuit 5, by an output voltage V2 of a pulse width modulating decoder 7 to be pulse-modulated by means of a data value inputted to a data input terminal group 12, a sample-and-hold switch 4 is closed, and a sample-and-hold capacitor 3 is charged. A constant current source reference change-over switch 6 selects a reference circuit 9 for a small current constant current source while the capacitor 3 at the OFF-time of the output voltage of the pulse width modulating decoder 7 is held, and it selects a reference circuit 8 for a large current constant current source while the capacitor 3 at the ON-time of the output voltage V2 is charged. Thus, the large current is applied through an output buffer 1 only when the capacitor 3 is charged, and the capacitor 3 can be driven at the energy consumption corresponding to the change of the output voltage.


Inventors:
SAITO TADASHI
Application Number:
JP11659088A
Publication Date:
November 17, 1989
Filing Date:
May 13, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03M1/66; H03K19/00; H03M1/82; (IPC1-7): H03M1/66
Domestic Patent References:
JPS62274930A1987-11-28
JPS62143518A1987-06-26
JPS6365714A1988-03-24
Attorney, Agent or Firm:
Naoki Kyomoto (3 outside)