PURPOSE: To provide a parallel arithmetic semiconductor integrated circuit device where the parallel degree of a processing with little addition circuits can be increased, a neural network can efficiently be simulated and data can be transferred at high speed between neuron units.

CONSTITUTION: Plural synapse units 9 including first circuits 2 executing the prescribed operation of a neuron state value input and a synapse load value and second arithmetic circuit 8 receiving the output of the first arithmetic circuit to one input are provided. The second arithmetic circuits are laterally connected and the output of the second arithmetic circuit in the final stage in the lateral connection is accumulated. Non-linear conversion is executed in a non-linear processor 4. The output of the non-linear processor 4 is fed back again to corresponding neuron state value input through prescribed connection paths 7-0, and 7-1.