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Title:
PARALLEL LIKELIHOOD ARITHMETIC UNIT
Document Type and Number:
Japanese Patent JPH03100600
Kind Code:
A
Abstract:

PURPOSE: To reduce the transfer quantity of a computed result and to make the capacity of a computed result memory circuit small by eliminating the computed result with low likelihood clearly recognized not being selected finally out of the computed results transferred to the computed result memory circuit in advance.

CONSTITUTION: A likelihood computation division circuit 1 divides likelihood computation for input data 5 into the one in small unit capable of performing a parallel processing, and a likelihood arithmetic circuit 2 executes divided likelihood computation, and a result outside threshold value elimination circuit 9 selects and outputs only the computed result 7c with likelihood higher than a designated threshold value 11. The computed result memory circuit 3 stores a selected computed result 7c, and a threshold value arithmetic circuit 10 designates the likelihood with Nth higher value out of stored likelihood as the threshold value 11 of the likelihood to the computed result memory circuit 3 with each new input of the computed result 7c. A computed result decision circuit 4 selects and outputs N results with higher likelihood out of the computed results 7b from all the stored computed results. Thereby, it is possible to reduce the transfer quantity of the computed result 7c, and to make the capacity of the computed result memory circuit 3 small.


Inventors:
IWASAKI TOMOHIRO
Application Number:
JP23768289A
Publication Date:
April 25, 1991
Filing Date:
September 13, 1989
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G10L15/34; (IPC1-7): G10L3/00
Attorney, Agent or Firm:
Kaneo Miyata (3 outside)



 
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