PURPOSE: To detect a fault of a phase modulating circuit easily by providing a circuit which makes a parity check on data after phase modulation and another circuit which selects its output at the timing of the phase modulation.

CONSTITUTION: Data (a) after phase modulation is parity-checked by a parity checking circuit 1 at parity check timing (b), and even and odd signal outputs (h) and (i) are inputted to a selecting circuit 4. To the selecting circuit 4, a timing signal (f) for phase modulation, the output (e) of a mode register 2 setting a various-mode input (c), and a signal (g) outputted from a timing generating circuit 3 by receiving the output (d) of the mode register 2 are inputted, thereby selectively outputting the outputs (h) and (i). If the number of high-level signals is odd at the data time of the signal (f) and even at the phase time, a parity error is discriminated. Thus, a fault of the phase modulating circuit 1 is detected easily.