PARTIAL STORAGE PROCESSING METHOD, MEMORY SYSTEM AND LARGE SCALE INTEGRATED CIRCUIT

Title:

PARTIAL STORAGE PROCESSING METHOD, MEMORY SYSTEM AND LARGE SCALE INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JP2001325147

Kind Code:

A

Abstract:

To reduce the segmentation delay of a succeeding request due to partial storage processing.

Merge selectors 150 to 157 for selecting fetched data and stored data, queues 160 to 167 for storing merged data, queues 130 to 137 for storing a request for instructing the writing of the merged data in each memory bank, and logical parts 180 to 187 for judging whether each memory bank is busy or not are included in respective memory banks 0 to 7. After merging the stored data and the fetched data, the merged data and a request for instructing the writing of the merged data in the corresponding memory bank are stored in each memory bank and the merged data stored in the non-busy memory bank are stored in the memory bank concerned in parallel with another succeeding request processing.

Inventors:

SAITO TAKESHI
HONMA KAZUKI
KUROKAWA HIROSHI

Application Number:

JP2000144526A

Publication Date:

November 22, 2001

Filing Date:

May 17, 2000

Export Citation:

Click for automatic bibliography generation Help

Assignee:

HITACHI LTD

International Classes:

G11C11/413; G06F12/00; G06F12/06; (IPC1-7): G06F12/06; G06F12/00; G11C11/413

Domestic Patent References:

JPS54109333A	1979-08-27
JPH01223541A	1989-09-06
JPH04175943A	1992-06-23
JPH04182984A	1992-06-30

Attorney, Agent or Firm:

Makoto Suzuki

Previous Patent: DATA STORAGE SYSTEM AND DATA BROADCAST TRANSMITTER/ RECEIVER USING THE SYSTEM

Next Patent: METHOD AND DEVICE FOR CONTROLLING ACCESS