Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PASSIVATION METHOD OF SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JPS6315424
Kind Code:
A
Abstract:

PURPOSE: To prevent the increase of leakage currents at a time when a semiconductor element is left as it is under the atmosphere of wet beat, and to improve reliability by using a specific polyamide acid and the mixture of a tertiary amine compound and a specific silanol compound and/or a partial condensate thereof as varnish.

CONSTITUTION: In a passivation method in which the exposed surface of a P-N junction in a semiconductor element is coated with polyimide group varnish and heated and treated, a polyamido acid having a structural unit shown in formula [I] and the mixture of a tertiary amido compound and an silanol compound shown in formula [II] and/or a partial condensate thereof are employed as varnish. Rl represents a trivalent or tetravalent organic group, R2 a bivalent organic group, m1 or 2, (R3) a monovalent organic group and n 1, 2, 3 in formulae. A compound capable of being changed into a polymer having an imido ring and other ring structure by heating or a proper catalyst is employed as the polyamido acid.


Inventors:
EGUCHI MASUICHI
HIRAMOTO YOSHI
MANABE SHINICHI
Application Number:
JP16017286A
Publication Date:
January 22, 1988
Filing Date:
July 08, 1986
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TORAY INDUSTRIES
International Classes:
H01L21/312; C09D179/08; (IPC1-7): H01L21/312
Domestic Patent References:
JPS6066437A1985-04-16



 
Previous Patent: Radio equipment and a radio system

Next Patent: MATTRESS SYSTEM