Title:
パターン形成方法及び半導体装置
Document Type and Number:
Japanese Patent JP5407192
Kind Code:
B2
Abstract:
A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.
Inventors:
Mitsuaki Igashi
Masahiro Sueda
Takase Toshio
Akihiro Hasushima
Masahiro Sueda
Takase Toshio
Akihiro Hasushima
Application Number:
JP2008161538A
Publication Date:
February 05, 2014
Filing Date:
June 20, 2008
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
H01L21/82; G03F1/68; G03F1/70; H01L21/027; H01L21/76; H01L21/8238; H01L27/08; H01L27/092
Domestic Patent References:
| JP2002289704A | ||||
| JP2003337843A | ||||
| JP11297853A |
Attorney, Agent or Firm:
Takeshi Hattori