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Title:
PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2002139842
Kind Code:
A
Abstract:

To provide a pattern forming method for a field effect transistor by which a resist layer having a two-layer structure can be exposed by a single exposure, good throughput is ensured and a gate of <0.1 μm having a stable sectional shape is obtained.

The pattern forming method includes a step for forming a first resist layer on a substrate, a step for forming a chemical amplification type second resist layer having higher sensitivity than the first resist layer on the first resist layer, a step for carrying out exposure in such a way that the first resist layer is sufficiently exposed and a step for successively developing the second resist layer and the first resist layer. An opening having a smaller size than an opening formed in the second resist layer is formed in the first resist layer.


Inventors:
KON JUNICHI
YANO EI
Application Number:
JP2000335138A
Publication Date:
May 17, 2002
Filing Date:
November 01, 2000
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G03F7/095; G03F7/004; G03F7/38; H01L21/027; (IPC1-7): G03F7/095; G03F7/004; G03F7/38; H01L21/027
Domestic Patent References:
JPH1197328A1999-04-09
JPH02264261A1990-10-29
JPH02253263A1990-10-12
JPH09270464A1997-10-14
JPS6155922A1986-03-20
JPS58218119A1983-12-19
JPS5646536A1981-04-27
JPH07220999A1995-08-18
JPS5731135A1982-02-19
JPH1167792A1999-03-09
JPH04269756A1992-09-25
Attorney, Agent or Firm:
Junichi Yokoyama