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Patent Searching and Data


Title:
PEAK HOLD CIRCUIT
Document Type and Number:
Japanese Patent JP2002232248
Kind Code:
A
Abstract:

To provide a peak hold circuit in which a stable long discharging time can be set without affected by the input impedance of a circuit connected to an output.

This peak hold circuit is provided with a transistor Q1 the base of which an input signal voltage is applied to, a transistor Q2 the base of which an output voltage is inputted to, a current source 1 connected to the emitters of Q1 and Q2 in common, a first current mirror circuit consisting of transistors Q3 and Q4 connected to the collector of Q1, a second current mirror circuit composed of transistors Q5 and Q6 connected to the collector of Q2, a capacitor CPH the one terminal of which is connected to the collector of Q4 and the other terminal of which is grounded, a transistor Q7 whose base is connected to one terminal of the CPH, a current source 2 for feeding a bias current of Q7, a transistor Q8 to the base of which the emitter of Q7 is connected and to the emitter of which an output voltage is connected, and a current source 3 for feeding a bias current to Q8.


Inventors:
NISHIKAWAJI TAMOTSU
Application Number:
JP2001030583A
Publication Date:
August 16, 2002
Filing Date:
February 07, 2001
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03G11/04; H03G11/00; (IPC1-7): H03G11/04; H03G11/00
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)