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Patent Searching and Data


Title:
PERIPHERAL EQUIPMENT CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS5659333
Kind Code:
A
Abstract:

PURPOSE: To enhance the reliability by doubly providing the controllers equipped with both the test input/output function and the peripheral interruption function, between CPU and the peripheral equipments.

CONSTITUTION: At the time of the process input/output by CPU, in case when abnormal has been detected, the test input/output are executed by use of the test input/output functions 7a, 7b of the controllers 4a, 4b from CPU5, and if the test input/output are normal, it is decided that the controllers 4a, 4b are normal and the process input/output units 1W3 are abnormal. On the other hand, if the test input/output are abnormal, it is decided that the process input/output units 1W3 are normal, and the controller 4a or 4b is abnormal, and thereafter, CPU executes the processing by the other controller without using the abnormal controller.


Inventors:
YOSHIDA YUUJI
Application Number:
JP13352379A
Publication Date:
May 22, 1981
Filing Date:
October 18, 1979
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F11/16; G06F3/00; G06F13/00; (IPC1-7): G06F3/00; G06F11/16