CONTROL CIRCUIT FOR THREE-LEVEL INVERTER

Japanese Patent JP3186369

B2

PURPOSE: To prevent an excessively high voltage from being applied across a circuit element by making the balancing control of an DC input capacitor effective even when no load is applied or a light load is applied and to make the discrimination of driving/braking unnecessary, and at the same time, to prevent the unbalance of a capacitor voltage from increasing.
CONSTITUTION: A control circuit for three-level inverter is provided three-phase quantities of serial circuits of first or fourth semiconductor switching element, the both ends of which are connected to a DC power source circuit, and first and second coupled diodes and the inverter is controlled in, for example, PWM. The control circuit is also provided with various means, such as a table 13, multipliers 14R, 14S, and 14T, adders 21R, 21S, and 21T, etc., for adding an even- order harmonic (e.g. sixth or second harmonic) of the fundamental frequency of the inverter to the output voltage of each phase of the inverter and various means, such as an adder 11, adjuster 12, multipliers 14R, 14S, 14T, etc., which detect the potential variation at the neutral point of the DC power source circuit based on the voltage deviation of a DC input capacitor and decide the magnitude of the even-order harmonics to be added to the output voltage commands based on the detected magnitude of the potential variation.

WO/2018/012028	POWER SUPPLY SYSTEM
JPH07128399	INSPECTION EQUIPMENT FOR INVERTER CIRCUIT

Shigeru Kamiya
Makoto Hashii
Hiroshi Suzuki
Hiroshi Osawa

JP24888393A

July 11, 2001

September 09, 1993

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Fuji Electric Co., Ltd.

H02M7/48; H02M7/483; H02M7/515; (IPC1-7): H02M7/48

JP2261063A
JP5227796A

Yuichi Morita

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