PURPOSE: To simplify the constitution greatly by obtaining pulse trains of N channels which are brought under the phase control of one storage circuit and 1st and 2nd counters.

CONSTITUTION: High-order addresses above an (M)th address are specified by the 2nd counter 14. The 1st M-ary counter 13 counts a clock from a terminal 15, outputs D1-DN of 1st-(N)th bits of the storage circuit 12 are latched by a latch circuit 16 with the clock from the terminal 15, and the circuit 16 outputs N desired pulses. When the counted value of the counter 13 varies, the output of the circuit 12 becomes unstable to generate a glitch, but the stable output of the circuit 12 is latched by the circuit 16 to remove this glitch. Consequently, the constitution is simplified extremely.