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Title:
PHASE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH0556091
Kind Code:
A
Abstract:

PURPOSE: To detect a phase accurately by providing a clock generator, a pseudo random pattern generator, a 1-2 series modulator, variable shift register and 2 systems of 4-phase modulator to the detection circuit.

CONSTITUTION: A band of a signal modulated by 4-phase modulators 14, 15 is set in matching with a band of demodulators 35, 36 of a reception system. A pseudo random pattern generator 2 outputs a base band signal based on a clock generator. The one signal is subject to 4-phase modulation by phase modulators 4, 5, a π/2 branching device 6, a local oscillator 7 and a synthesizer 8. The other signal is given to a variable shift register 9, in which the signal delay time is in matching with a delay time of a delay line 41 and the signal is modulated by the 4-phase modulator 15 of the same configuration as the modulator 14. The signals are respectively inputted to demodulators 35, 36 via π/2 branching devices 33, 34 to detect a phase difference. The delay time difference of the two modulation signals is zero at the center frequency. Furthermore, since an echo at the side band is subject to reflection phase averaging, a ripple component is less and the phase of a true value is detected.


Inventors:
TANABE SHINJI
FUJIMOTO YOSHIYUKI
Application Number:
JP20971891A
Publication Date:
March 05, 1993
Filing Date:
August 22, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04B7/02; H04B7/08; H04L27/18; (IPC1-7): H04B7/02; H04B7/08; H04L27/18
Attorney, Agent or Firm:
Uchihara Shin



 
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