PURPOSE: To attain more accurate signal processing by providing a delay circuit having a delay time equivalent to a phase difference between 1st and 2nd signals to a pre-stage of a signal processing circuit to which the 1st signal is led.

CONSTITUTION: A synchronizing separator circuit 1 separates a horizontal synchronizing signal HD from an introduced reproduction luminance signal Y and the separated horizontal synchronizing signal HD is led to a PLL circuit 2 as a comparison signal. The PLL circuit 2 compares the phase of a reference signal generated internally with the phase of a comparison signal and outputs a clock WCK including jitter of the comparison signal to a write address counter 3 as a write clock. A delay circuit 10 retards the introduced reproduction luminance signal Y by a prescribed delay time T0 and gives it to a memory 5 via an A/D converter 4. The delay time T0 is set to a time resulting from one regular horizontal period t0 and a response delay time when the PLI circuit 2 generates the write clock WCK from the horizontal synchronizing signal HD.