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Patent Searching and Data


Title:
PHASE LOCKED OSCILLATING CIRCUIT
Document Type and Number:
Japanese Patent JPH01218215
Kind Code:
A
Abstract:

PURPOSE: To obtain a transmission circuit without generating the pull out at the time of switching an input signal by providing a delay circuit to delay the gain increase of the loop filter at the time of switching an input switching circuit, for a prescribed time.

CONSTITUTION: In a phase locked oscillating circuit, when a SERVO MODE signal is shifted from a turn-off condition A to a turn-on condition, a READ PULSE signal 54 outputted through a switching circuit 16 is inputted to a data latch circuit 11 and a monostable multivibrator 12, output signals 31 and 32 of these circuits are impressed to a pulse-control voltage converter and a loop filter 13. Here, the signals 31 and 32 are the ones in which the phase is dislocated, the gain of the filter 13 at this time is the comparatively low one while a HIGH GAIN signal 52 is delayed for about a 2-bit time by delay circuit 17, and therefore, more or less control voltage 33 is fluctuated and the change of the control voltage can be comparatively minimized. Thereafter, when the signal 52 is impressed and becomes a condition C, the gain of the filter 13 becomes larger and a quick pull in action can be executed.


Inventors:
MATSUMURA NOBUHIRO
Application Number:
JP4230888A
Publication Date:
August 31, 1989
Filing Date:
February 26, 1988
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03L7/14; G11B20/10; (IPC1-7): G11B20/10; H03L7/14
Attorney, Agent or Firm:
Masami Akimoto