Title:
PICTURE DISPLAY DEVICE
Document Type and Number:
Japanese Patent JP3430961
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enable a picture display device to perform a high-speed arithmetic operation, and to prevent a waiting state of a processor from occurring due to operating state of a picture memory, by controlling matrix connections so that drawing-operated data are written in the memory presenting the state in which data have already been outputted for display.
SOLUTION: This picture display device is provided with graphic controllers(GC) 61-63 which are connected to a CPU 51 managing the control of the whole device via a common bus 55 and perform prescribed drawings, video RAMs(VRAM) 81-84, and a multiplexer(MUX) 70 for switching correspondences between these plural GC and the VRAMs. And CPU 51 communicates with CG 61-63, and outputs drawing data to GC which have completed drawing operation. Namely, for example, CG 61 receives drawing data from CPU 51 and recognizes VRAM 84, which has already completed displaying, as memory for own drawing for this time, and clears the whole memory area of VRAM 84 before starting frame-drawing.
Inventors:
Mokichi Higo
Application Number:
JP7318499A
Publication Date:
July 28, 2003
Filing Date:
March 18, 1999
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G06F3/153; G09G5/36; G09G5/373; G09G5/393; G09G5/397; G09G5/399; (IPC1-7): G09G5/393; G06F3/153; G09G5/36; G09G5/397; G09G5/399
Domestic Patent References:
| JP197988A | ||||
| JP59222884A | ||||
| JP2206881A | ||||
| JP6250810A |
Attorney, Agent or Firm:
Kaneo Miyata (1 person outside)