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Title:
PICTURE DISPLAY SYSTEM
Document Type and Number:
Japanese Patent JPS6352235
Kind Code:
A
Abstract:

PURPOSE: To give no influence to such a process having high priority as a display action, etc., when a frame buffer memory is shared by a display controller and other bus master modules, by providing a controller to a master module to indicate propriety of an access to be given to the frame buffer memory.

CONSTITUTION: When a display controller which performs the display of pictures is executing such a process having high priority as a picture display action, etc., an instruction signal showing an executing state of said display action is given to the display controller. At the same time, the accesses given to a frame buffer memory FBM from other bus master modules are inhibited. Then an instruction signal showing that the display controller is executing an action having low priority is given to said controller to permit accesses given to the FBM given from other bus master modules. Thus it is possible to perform arbitration of accesses to the FBM among bus master modules included in a picture display system.


Inventors:
YOKOTA YOSHIKAZU
SATO JUN
YOSHIDA SHIGEAKI
TAKEDA HIROSHI
Application Number:
JP19535586A
Publication Date:
March 05, 1988
Filing Date:
August 22, 1986
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F3/153; G06F13/20; G06F13/36; (IPC1-7): G06F3/153; G06F13/20
Attorney, Agent or Firm:
Katsuo Ogawa



 
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