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Title:
PICTURE DISPLAY UNIT
Document Type and Number:
Japanese Patent JPS5447420
Kind Code:
A
Abstract:

PURPOSE: To secure effective display through an interrelation even for the picture element information of different picture element capacities, by dividing a picture into N×M blocks corresponding to the addresses of the picture memory.

CONSTITUTION: Picture memory 11 consists of N×M blocks composed of n×m picture elements. With supply of the address designation signal to multiplexer 12 from CPU, multiplexer 12 is analyzed into the row and column addresses to carry out the address designation for memory 11. Through this address designation, the picture information representing the n×m picture elements of the block are written into each address from CPU through the address designation like (0,0), (0,1), (1,0) and (1,1) and then read out by the scanning clock synchronized with the display scan of the monitor. Thus, the effective display is ensured through an interrelation even for the picture information of different picture element capacities


Inventors:
IMAMURA MAKOTO
Application Number:
JP11386177A
Publication Date:
April 14, 1979
Filing Date:
September 21, 1977
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H04N7/18; A63F13/52; A63F13/55; G06F12/02; G06T3/40; G09G5/00; G11C7/00; G11C8/00; (IPC1-7): G11C7/00; H04N7/18



 
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