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Title:
PICTURE ELEMENT ARRANGEMENT DISPLAY DEVICE
Document Type and Number:
Japanese Patent JPH07129125
Kind Code:
A
Abstract:

PURPOSE: To restrain the occurrence of a difference in brightness caused by a delay of a sampling pulse signal and the deterioration of contrast.

CONSTITUTION: Digital R, G and B signals are supplied to respective ones of D/A converting circuits 71 and 72 from a memory 6. The D/A converting circuit 71 performs D/A conversion on the digital R, G and B signals in response to a clock signal CLK10, and supplies first analog R, G and B signals R10, G10 and B10 for odd number order arrangement picture elements of a liquid crystal panel 3 to first and second horizontal drivers 11 and 12. The D/A converting circuit 72 performs D/A conversion on digital R, G and B signals in response to a clock signal CLK20, and supplies second analog R, G and B signals R20, G20 and B20 for even number order arrangement picture elements of the liquid crystal panel 3 to third and fourth horizontal drivers 13 and 14. Thereby, the first and the second analog R, G and B signals are supplied to the respective horizontal drivers 11 and 12 as a DC voltage waveform or a waveform close to a rectangular wave.


Inventors:
SASAKI TORU
Application Number:
JP27251093A
Publication Date:
May 19, 1995
Filing Date:
October 29, 1993
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
G02F1/133; G09G3/20; G09G3/36; H04N5/66; (IPC1-7): G09G3/36; G02F1/133; G09G3/20; H04N5/66
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)



 
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