Title:
PIN MOUNTING STRUCTURE OF PIN GRID ARRAY
Document Type and Number:
Japanese Patent JPS6240754
Kind Code:
A
Abstract:
PURPOSE: To reduce the thickness and cost of a pin grid array by interposing a film substrate and a wiring pattern between the step and the head the head of the stepped pin engaged within a through hole of the substrate.
CONSTITUTION: A stepped pin 2 has a large-diameter portion 2a for forming a step near one end side, the one end side is engaged with a through hole 7 of a film substrate 1, and the one end side is then calked to form a head 2b. A metal ring 8, the substrate 1 and a wiring pattern 6 are interposed between the head 2b and the portion 2a to be secured to the substrate 1, and electrically connected with the pattern 6. Thus, a pin grid array of the substrate made of plastic film can be manufactured.
More Like This:
Inventors:
KONISHI AKIRA
WAKANO TERUO
WAKANO TERUO
Application Number:
JP18090285A
Publication Date:
February 21, 1987
Filing Date:
August 16, 1985
Export Citation:
Assignee:
DAI ICHI SEIKO CO LTD
International Classes:
H01L23/12; H01L23/28; H01L23/48; H01L23/50; (IPC1-7): H01L23/12; H01L23/28; H01L23/48
Attorney, Agent or Firm:
Aoyama
Previous Patent: Time sharing double Trust (TDD) uplink down-link (UL-DL) reconstruction
Next Patent: SUBSTRATE FOR CONNECTING SEMICONDUCTOR DEVICE
Next Patent: SUBSTRATE FOR CONNECTING SEMICONDUCTOR DEVICE