Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PIPELINE ADC FOR PERFORMING DIGITAL SELF CALIBRATION, AND ITS METHOD
Document Type and Number:
Japanese Patent JP2005304033
Kind Code:
A
Abstract:

To provide a pipeline analog-digital converter for performing digital self calibration, and its method.

The pipeline ADC for converting an analog input signal to a digital output signal includes a plurality of analog-digital converting units to be cascade-connected so as to form a pipeline including a plurality of digital output terminals, a calculation unit coupled to the analog-digital converting units and for producing a plurality of calibration parameters in response to a signal of a digital output terminal within a first mode, and a calibration unit coupled to the calculation unit and the analog-digital converting units and for calibrating the signal of the digital output terminal in response to the calibration parameter within a second mode so as to produce the digital output signal.


Inventors:
TSAI JUI-YUAN
WANG WEN-CHI
CHIANG CHIA-LIANG
LEE CHAO-CHENG
Application Number:
JP2005113288A
Publication Date:
October 27, 2005
Filing Date:
April 11, 2005
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
REALTEK SEMICONDUCTOR CORP
International Classes:
H03M1/14; H03M1/10; H03M1/12; H03M1/38; (IPC1-7): H03M1/14; H03M1/10
Attorney, Agent or Firm:
Masaru Sato