PURPOSE: To provide a pipeline arithmetic processor capable of executing proper processing in accordance with the contents of information and efficiently utilizing a pipeline.

CONSTITUTION: Input data to be inputted to the pipeline arithmetic processor 5 are constituted of information data D detected by a sensor S and discrimination data R consisting of flags indicating the priority of the data D and a valid/ invalid flag indicating the validity of the information. Plural input data are inputted to a priority discriminator 6 in parallel through plural input registers-(r), the data with the highest priority out of data having the valid flag is selected based upon the discrimination data, its information data Dij is inputted to a fuzzy inference engine core 7 and its decision data Rij is inputted to a delay device 8. The former data Dij is processed by pipeline processing and its result data Cij are outputted, so that the data Rij making a pair with the result data Cij are delayed only by the processing time by the device 8 and outputted simultaneously with the data Cij.