Title:
PIPELINE ARITHMETIC UNIT
Document Type and Number:
Japanese Patent JP3776644
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce a hardware quantity and power consumption.
SOLUTION: This unit is provided with stage latch circuits 1101 and 2101 provided in the input step of a first arithmetic stage for holding first data SOURCE1 to be operated and second data to be operated, computing element 1201 provided on the first arithmetic stage for performing operation while using the first data SOURCE1 to be operated and the second data to be operated, stage latch circuit 1102 provided between first and second arithmetic stages for holding the output value of the computing element 1201 computing element 1202 provided on the second arithmetic stage for performing operation while using the value of the stage latch circuit 1102 when an instruction INST2 is decoded, and instruction decoder 3201 for decoding the instruction INST2 to the computing element 1201 as a through instruction SRC1 for passing through the value of the stage latch circuit 1101 (the first data SOURCE1 to be operated).
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Inventors:
Akihiko Owada
Application Number:
JP28485099A
Publication Date:
May 17, 2006
Filing Date:
October 05, 1999
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F9/38; G06F9/30; (IPC1-7): G06F9/38
Domestic Patent References:
| JP58106636A | ||||
| JP200066894A | ||||
| JP200010780A |
Attorney, Agent or Firm:
Hiroaki Sakai
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