Title:
PLL CIRCUIT FOR INFORMATION REPRODUCING DEVICE
Document Type and Number:
Japanese Patent JPS6423467
Kind Code:
A
Abstract:
PURPOSE:To prevent out of synchronism of a PLL at missing of a reproducing signal and at restoration by holding a recovered clock frequency and phase just after missing of the reproducing signal, releasing the holding after the restoration of the reproducing signal and adjusting the sensitivity of the PLL to a required value. CONSTITUTION:If a reproducing signal is missing, the output S1 of a reproducing signal missing detection circuit 4 goes to H, a sampling and holding circuit 5 provided to a PLL holds the frequency and phase of the recovered clock just after the missing to prevent out of synchronism of the PLL at the reproducing signal missing. The holding of the circuit 5 is released similarly at the restoration of the reproducing signal and a switching output S3 from a switching signal generating circuit 7 goes to H, switches SW1, SW2 for an LPF2 and an attenuator 6 are changed over, the sensitivity of the PLL is brought into a low level, then the out of synchronism at the restoration of the reproducing signal is prevented without the effect of the overshoot characteristic of the PLL. When a phase error goes within a prescribed value, the switches SW1, SW2 are changed over similarly and the sensitivity of the PLL is brought into a high level.
Inventors:
HOSOYA HIDEKI
Application Number:
JP17966787A
Publication Date:
January 26, 1989
Filing Date:
July 17, 1987
Export Citation:
Assignee:
CANON KK
International Classes:
G11B20/14; G11B7/00; G11B7/005; H03L7/08; H03L7/093; H03L7/14; (IPC1-7): G11B7/00; G11B20/14; H03L7/08; H03L7/14
Attorney, Agent or Firm:
Yamashita