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Title:
POLISHING METHOD FOR SEMICONDUCTOR SUBSTRATE
Document Type and Number:
Japanese Patent JPH09134904
Kind Code:
A
Abstract:

To accurately control a polishing thickness to uniformly polish ever in the case of polishing a plurality of semiconductor substrates at the same time.

In an initial polishing stage, a voltage having such a level that prevents formation of a passivity film in a semiconductor substrate 3 is applied between the semiconductor substrate 3 and a polishing disc 1. When the thickness reaches a prescribed value, the application voltage is raised to form the passivity film on a surface of semiconductor substrate 3 in contact with the polishing disc 1. Since the passivity film is slower in polishing rate than the original semiconductor substrate 3, the formation position of the passivity film can be set at the polishing termination position. This eliminates the need for formation of an oxide film stopper in the semiconductor substrate 3, thereby enabling prevention of development of crystalline defects and warpage of the semiconductor substrate 3. Further, polishing during application of the voltage enables prevention of formation of a micropyramid and at the same time, enables realization of improvement in the polishing rate based on electrochemical etching effect.


Inventors:
KUSUYAMA KOICHI
IWASAKI YASUKAZU
UCHIYAMA MAKOTO
Application Number:
JP29122895A
Publication Date:
May 20, 1997
Filing Date:
November 09, 1995
Export Citation:
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Assignee:
NISSAN MOTOR
International Classes:
B24B1/00; B24B37/013; B24B37/04; B81C1/00; H01L21/304; H01L21/306; H01L21/3063; (IPC1-7): H01L21/306; B24B1/00; B24B37/04; H01L21/304; H01L21/3063
Attorney, Agent or Firm:
Fuyuki Nagai