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Patent Searching and Data


Title:
POLISHING METHOD FOR SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPH042466
Kind Code:
A
Abstract:

PURPOSE: To drastically reduce the generation of the crack, chip, etc., of a wafer at the initial stage of polishing, by polishing with the polishing pressure being set lower at the initial stage of polishing.

CONSTITUTION: Pressure is concentrically applied only on few wafers in a large thickness at the initial stage of polishing and at this time polishing is performed by setting the polishing pressure lower than the ordinary. So, no excessive pressure is applied on these wafers and the inconvenience generation of crack, chip, etc., can be restrained. At the later stage of polishing the thicknesses of each wafers are aligned and the state of the pressure being applied uniformly is obtained. Consequently, the polishing pressure on the whole is set at the specific value higher than that at the initial stage and the averaged pressure applied on the wafer becomes in an adaptive size.


Inventors:
NAKAYAMA MASAHIRO
Application Number:
JP9910690A
Publication Date:
January 07, 1992
Filing Date:
April 13, 1990
Export Citation:
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Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
B24B37/00; B24B37/005; H01L21/304; (IPC1-7): B24B37/00; H01L21/304
Attorney, Agent or Firm:
Tetsuji Ueshiro