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Patent Searching and Data


Title:
POLYCIDE WIRING, METHOD OF FORMING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2003100748
Kind Code:
A
Abstract:

To reinforce a predetermined region near the boundary between a P-type polysilicon film and an N-type polysilicon film by a minimum space to prevent breaking and high resistance of polycide wiring.

First N-type impurity of a first dosage is introduced on the entire surface of a silicon film deposited on a semiconductor substrate via an insulating film, and second N-type impurity of a second dosage is introduced on a first area of the silicon film while a second area is masked. Subsequently, in a connection region including the boundary between the first and second areas, patterning is performed on the silicon film so as to have a width wider than areas on the both sides. Then, P-type impurity of a third dosage larger than the first dosage is introduced only on the second area of the silicon film, high melting point metal film is deposited on the silicon film to form a silicide film, and thus the polycide wiring is formed.


Inventors:
OCHI TSUNEO
KIMURA YOSHITAKA
Application Number:
JP2001286544A
Publication Date:
April 04, 2003
Filing Date:
September 20, 2001
Export Citation:
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Assignee:
KAWASAKI MICROELECTRONICS KK
International Classes:
H01L21/28; H01L21/3205; H01L21/8238; H01L23/52; H01L27/092; H01L29/423; H01L29/43; H01L29/49; (IPC1-7): H01L21/3205; H01L21/28; H01L21/8238; H01L27/092; H01L29/43
Attorney, Agent or Firm:
Nobuto Watanabe (1 person outside)