Title:
POWER CIRCUIT
Document Type and Number:
Japanese Patent JP3695305
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent a large current from flowing owing to variance of a process, etc., by controlling the operations of a P-channel transistor and an N- channel transistor of the output stage in a power circuit which drives a load on a push-pull basis.
SOLUTION: This circuit is equipped with a 1st amplification path 10 which inputs a 1st potential and supplies a current to an output terminal when a control signal is in a 1st state, a 2nd amplification path 20 which inputs a 2nd potential and absorbs a current from the output terminal when the control signal is in a 2nd state, an intermediate-potential generating circuit which generates a 3rd potential between the 1st and 2nd potentials, and a comparing circuit 30 which compares the 3rd potential with the potential at the output terminal with each other to generate and supplies the control signal to the 1st and 2nd amplification paths.
Inventors:
Takashi Fujise
Application Number:
JP2000312392A
Publication Date:
September 14, 2005
Filing Date:
October 12, 2000
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G05F3/24; H03F3/30; H03F3/45; H03F3/68; G05F3/26; (IPC1-7): G05F3/26; H03F3/30; H03F3/45; H03F3/68
Domestic Patent References:
| JP9203885A | ||||
| JP61274511A | ||||
| JP7230073A | ||||
| JP2059806A |
Attorney, Agent or Firm:
Mutsumi Yanase
Masaaki Utsunomiya
Masahiko Ueyanagi
Osamu Suzawa
Masaaki Utsunomiya
Masahiko Ueyanagi
Osamu Suzawa