Title:
POWER-ON RESET CIRCUIT FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3752107
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a power-on reset circuit for integrated circuit which can be formed within a small chip layout area and is suitable for a high-density integrated circuit.
SOLUTION: This circuit is provided with a reset circuit 100 and a delay circuit 200. The reset circuit 100 generates a reset signal VCCOK. The delay circuit 200 generates a signal VON delaying the reset signal VCCOK. The reset signal VCCOK is maintained in a first logic state until a power supply voltage VCC reaches a prescribed level. When the power supply voltage VCC reaches the prescribed level, the reset signal VCCOK is turned into second logic state. Then, after delay by the delay circuit 200, the reset circuit 100 is made inactive by the delay signal VON. Further, the reset signal VCCOK is maintained in the second logic state by the delay signal VON.
Inventors:
Choi Koh
Park Bell
Park Bell
Application Number:
JP16438699A
Publication Date:
March 08, 2006
Filing Date:
June 10, 1999
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H03K17/00; H03K17/22; H03K17/284; (IPC1-7): H03K17/22
Domestic Patent References:
| JP10041799A | ||||
| JP10079655A | ||||
| JP9200019A | ||||
| JP3249817A | ||||
| JP3175723A | ||||
| JP5045623A | ||||
| JP1144925U |
Foreign References:
| US4633107 |
Attorney, Agent or Firm:
Makoto Hagiwara