Title:
POWER-ON RESETTER
Document Type and Number:
Japanese Patent JP3025921
Kind Code:
B2
Abstract:
PURPOSE: To provide a circuit in which malfunction scarcely occurs so as to eliminate the operation of again outputting a reset signal due to a power source change, etc., in a conventional circuit, where a power-on resetter for generating a reset signal at a power source voltage to become stable after the power source is turned ON, by utilizing variations in resistance values of a MOS transistor in OFF and ON states.
CONSTITUTION: A voltage Vb generated by MOS transistors 1, 2 and a resistor 3 is input to a first input terminal of a voltage comparator 6, a voltage Va generated at resistors 4, 5 is input to a second input terminal of the comparator 6, an output of reset release is sent when a potential difference of the Vb, Va is inverted, a MOS transistor 9 is turned from OFF to ON by the output, the Vb is fed to a power source voltage side, the Va is fed to a ground potential side to form a circuit in which malfunction scarcely occurs due to a power source change.
Inventors:
Youichi Seshita
Yoshiaki Kitamura
Yoshiaki Kitamura
Application Number:
JP22636691A
Publication Date:
March 27, 2000
Filing Date:
August 13, 1991
Export Citation:
Assignee:
NEC Engineering Co., Ltd.
International Classes:
G06G7/14; H01L21/8234; H01L27/06; H03K17/22; (IPC1-7): H03K17/22; G06G7/14; H01L21/8234; H01L27/06
Domestic Patent References:
| JP3141415A | ||||
| JP3154116A | ||||
| JP27615A |
Attorney, Agent or Firm:
Masaki Yamakawa
Previous Patent: 複数物品結束包装材
Next Patent: ALARM OUTPUT DIAGNOSTIC AND SAFETY DEVICE FOR BURGLAR PREVENTING SENSOR
Next Patent: ALARM OUTPUT DIAGNOSTIC AND SAFETY DEVICE FOR BURGLAR PREVENTING SENSOR