Title:
POWER SUPPLY SOURCE AND SELF-DESTRUCTION TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3529635
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To securely inhibit the memory contents of a semiconductor integrated circuit from being fraudulently altered.
SOLUTION: A connection lead 28a is provided on the surface of the positive electrode collector and terminal plate 21 of the power supply source 6a, which is mounted on the element surface of an IC chip 12 so that the positive electrode collector and terminal plate 21 faces the integrated circuit. The connection lead 28a is connected to an electrode pad 10a of the IC chip 12a to electrically connect the positive electrode collector and terminal plate 21 to IC chip 12a. A metal thin film 29 placed covering the power supply source 6a is connect an electrode pad 10b of the IC chip 12 to electrically connect a negative electrode collector and terminal plate to the IC chip 12a.
Inventors:
Ogawa, Shigeo
Henmi, Manabu
Machida, Katsuyuki
Masashiro, Takahisa
Henmi, Manabu
Machida, Katsuyuki
Masashiro, Takahisa
Application Number:
JP22281098A
Publication Date:
May 24, 2004
Filing Date:
August 06, 1998
Export Citation:
Assignee:
NIPPON TELEGR & TELEPH CORP <NTT>
International Classes:
G06K19/07; G06F21/75; G06F21/86; G06K19/077; G06K19/10; G11C5/14; H01L21/822; H01L27/04; (IPC1-7): G06K19/07; G06K19/077; G06K19/10; G11C5/14; H01L21/822; H01L27/04
Attorney, Agent or Firm:
山川 政樹
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