PREPARATION OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Japanese Patent JPH06232250

A

PURPOSE: To further simplify formation of an insulating material layer on a wall of a recess by forming the recess only in one major surface of a slice and forming the insulating material layer prior to the division of the slice. CONSTITUTION: A p-n junction 2 is formed to be extended parallel to major surfaces 3 and 6 in a slice 1 of semiconductor material, a recess 4 is made in the major surface 3 for cutting of the p-n junction 2 to form mutually independent p-n junctions 2a, 2b, 2c, the slice 1 is divided at the recess position into a plurality of individual semiconductor bodies 10 having the p-n junctions 2a and 2b, and an insulating material layer 5 is formed on a wall of a recess 4. Thereby the formation of an insulating material layer 5 on the wall of the recess 4 can be carried out in such a simple manner that the insulating material layer 5 is formed on all the recesses 4, before the slice 1 is cut into the individual semiconductor bodies 10. Processing of a single semiconductor material slice 1 is much easier than processing of numerous individual semiconductor bodies 10.

JPH02119173	SEMICONDUCTOR DEVICE
WO/2008/134148	JUNCTION FIELD EFFECT TRANSISTORS IN GERMANIUM AND SILICON-GERMANIUM ALLOYS AND METHOD FOR MAKING AND USING
JPS55160447	SEMICONDUCTOR INTEGRATED CIRCUIT

HEERUTO YOHANESU DEYUINKERUKEN
YOZEFU PETERU KARURU HOTSUFUSU
YOSEFU PETORUSU KAIZAA

JP32867493A

August 19, 1994

December 24, 1993

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PHILIPS ELECTRONICS NV

H01L21/761; H01L21/301; H01L21/76; H01L21/78; H01L25/07; (IPC1-7): H01L21/76

Akihide Sugimura (5 outside)

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