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Patent Searching and Data


Title:
PROCESSOR AND INSTRUCTION EXECUTION METHOD
Document Type and Number:
Japanese Patent JPH03137747
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need of interposing a monitoring program by providing a non-previlege instruction capable of copying the page of data from a virtual source address to a virtual destination address by virtual addressing.

CONSTITUTION: When MVPG instruction is executed, the data present in a specified source page location are copied to a specified destination page location. A logic address is a virtual address(VA) or a real address and depends on whether '1' is set or '0' is set to a DAT bit in a PSW at present. LAs are in the same form both at a source and a destination, that is they are both the virtual addresses or the real addresses, and are as indicated by the state of the DAT bit of the PSW. By copying the page of the source location of an MS or and ES to the page of the destination location of the MS or the ES every time the MVPG instruction is executed, one page is copied.


Inventors:
JIYOFUREI OOEN BURANDEI
DEEBITSUDO BURUUSU EEMESU
RONARUDO FURANKURIN HIRU
DEEBITSUDO BURUUSU RINDOKUISUT
KENISU AANESUTO PURABETSUKU
KIYASUPAA ANSONII SUKARUCHI
RICHIYAADO JIYON SHIEMARUTSU
Application Number:
JP24766990A
Publication Date:
June 12, 1991
Filing Date:
September 19, 1990
Export Citation:
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Assignee:
IBM
International Classes:
G06F12/10; G06F12/14; (IPC1-7): G06F12/10
Attorney, Agent or Firm:
Koichi Tonmiya (1 person outside)