Title:
PRODUCTION OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5368990
Kind Code:
A
Abstract:
PURPOSE:To reduce use area without decreasing the operating speed of the gate circuit of an I<2> L and make perfect the electrical isolation between each gate circuit by providing the interelement isolating regions composed of the combination of an oxide and a high impurity concentration region in a vertical direction from the epitaxial layer surface down to the buried layer.
More Like This:
| JPS52133758 | SEMICONDUCTOR INTEGRATED CIRCUIT |
| JPS63169121 | MULTI-VALUE THRESHOLD LOGICAL CIRCUIT |
Inventors:
INOUE OSAMU
MORITA YOSHINORI
FUNATSU TSUNEO
MORITA YOSHINORI
FUNATSU TSUNEO
Application Number:
JP14504576A
Publication Date:
June 19, 1978
Filing Date:
December 01, 1976
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/8226; H01L21/331; H01L21/76; H01L27/082; H01L29/70; H01L29/73; H03K19/08; (IPC1-7): H01L21/76; H01L29/70; H03K19/08
Domestic Patent References:
| JPS5154379A | 1976-05-13 | |||
| JPS4736785A | 1972-11-29 | |||
| JPS5164386A | 1976-06-03 |