PURPOSE: To replace an optional instruction with a break instruction with switching of a data bus and to temporarily stop a program when a debugging job is carried out by a device using a processor.

CONSTITUTION: An address comparator circuit 7 compares with supervision the address value of an address bus 4 of a processor 1 with the address value held by a comparison address setting register 8. When the coincidence is secured between both address values, a bus switch signal 11 is outputted to a data bus gate 13 and a data bus transceiver 12 respectively. A break instruction of a break instruction setting register 10 is outputted to a data bus 6, and the instruction read out of a ROM 2 or a RAM 3 and inputted to the processor 1 is replaced with a break instruction. This break instruction stops temporarily a program and then the contents of a processor bus state holding register 9 are analyzed. Thus, the program is debugged.