To provide a method of manufacturing a resistance memory cell, including a process for forming a lower electrode, a process for forming a lower mask including a current suppression region, a process for forming a programmable resistance layer, a process for forming an upper mask including the current suppression region, and a process for forming an upper electrode.

The programmable resistance memory cell includes the lower electrode 20, the programmable resistance layer 22, and the upper electrode 24. The lower mask 21 is arranged between the lower electrode and the programmable resistance layer. The upper mask 23 is arranged between the programmable resistance layer and the upper electrode. The lower and upper masks include the current suppression region.

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