Title:
PROGRAMMABLE TIMING CIRCUIT FOR INTEGRATED CIRCUIT DEVICE HAVING TEST ACCESS PORT
Document Type and Number:
Japanese Patent JP3221633
Kind Code:
B2
Abstract:
PURPOSE: To obtain a programmable and controllable variable timing generating circuit.
CONSTITUTION: A programmable and controllable timing circuit(CTC) is formed on an integrated circuit chip(IC) having a TAP access pin(TAP) incorporating a TAP data input(TDI) pin, a TAP data output(TDO) pin, a TAP mode selection(TMS) pin, and a TAP clock(TCK) pin. The port TAP incorporates many TAP data registers TDRs connected so as to shift data signals received through the TDI pin to the TDO pin. A TAP instruction register TIR is connected so as to receive instruction codes from the TDI pin and command the use of a selected TDR. A TAP controller is connected so as to receive control signals from the TMS pin and clock signals from the TCK pin and supply control signals and clock signals for controlling the actions of the TIR and TDRs.
Inventors:
John Earl Andrews
Application Number:
JP6488093A
Publication Date:
October 22, 2001
Filing Date:
March 02, 1993
Export Citation:
Assignee:
NATIONAL SEMICONDUCTOR CORPORATION
International Classes:
G01R31/3185; G04F1/00; G01R31/28; H03K7/08; H03M1/82; (IPC1-7): G01R31/28
Domestic Patent References:
| JP4211842A | ||||
| JP4204274A | ||||
| JP63236409A |
Attorney, Agent or Firm:
Sumio Takeuchi (2 outside)
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