To secure a write recovery time margine by a method wherein a word line enable signal and a sense amplifier enable signal are concurrently produced using a write enable signal and an address transition retrieval pulse.

A logic operation part 206 logic-operates an address transistion pulse ATP and a pulse via a pulse extension part 106 of ATP to output two pulses. A switching part 306 outputs one pulse out of two pulses output from the operation part 206 corresponding to a write enable signal WEB. A logic operation part 406 logic-operates the output pulse from the switching part 306 and-WEB, concurrently produces a word line enable signal and a sense amplifier enable signal, and outputs respectively. Thus, it is possible to reduce an access time of data stored in a memory cell in a readout cycle and to secure a write recovery time margine.