Title:
PULSE MODULATION ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP3177636
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To execute a parallel arithmetic operation by a large-scaled input signal with a few elements and low energy consumption by integrating current pulses generated corresponding to an outside input signal, and converting them into charges, converting the amounts of the integrated charges into a binary digital signal, and outputting it.
SOLUTION: A pulse width modulation(PWM) signal 1 is inputted to a switched current source 2, and constant currents are generated only in a pulse width time, and converted into current pulses. The (n) pieces of current pulses are overlapped on a common current bus 3, and full charge amounts in proportion to the total sum of the input pulse width are obtained by a capacity integration method by a reference charge counting circuit(CPC1) 6. Excess charges generated as a quantization error are digitized on a time axis by a charge/time converting circuit(CTC) 7 so that the time resolution of the arithmetic operation is improved. Those digitized values are weighted and added in a digital area by using digital counter circuits 8 and 9, and outputted as a binary digital signal as the added result of the PWM signal 1.
Inventors:
Mu Iwata
Makoto Nagata
Makoto Nagata
Application Number:
JP2280497A
Publication Date:
June 18, 2001
Filing Date:
February 05, 1997
Export Citation:
Assignee:
Hiroshima University Dean
International Classes:
H03M1/50; G06G7/161; (IPC1-7): G06G7/161; H03M1/50
Domestic Patent References:
| JP5145420A | ||||
| JP5582846U |
Attorney, Agent or Firm:
Takehiko Suzue (5 outside)