PURPOSE: To perform a test even against a high speed circuit to be tested having the minimum operation period being shorter than the minimum test period of a testing clock, by generating independently two clock pulse signals, adjusting a phase so that waveforms of these two clock pulse signals are not superposed, taking OR, and using it as a clock.

CONSTITUTION: A clock pulse signal 42 which is generated by a first clock pulse generating circuit 24, and a clock pulse signal 43 which is generated by a second clock pulse generating circuit 25 and has passed through a phase adjusting circuit 26 are supplied to an OR circuit 30 having a high response speed, and outputted as a testing clock signal 44. Also, when a partial period 54 of a testing clock signal 53 is adjusted continuously by the phase adjusting circuit 26 of a pulse synthesizing circuit 21, it can be made shorter than the minimum operation period of a circuit to be tested 23, since the OR circuit 30 has a high response speed. Accordingly, by adjusting the partial period 54 of this testing clock signal 53 so as to be made equal to the minimum operation period of the circuit to be tested 23, its minimum operation period can be tested.