Title:
PULSE WIDTH MODULATING CIRCUIT
Document Type and Number:
Japanese Patent JP3298959
Kind Code:
B2
Abstract:
PURPOSE: To easily provide a pulse width modulating circuit by a simple constitution by adjusting a time difference generated between set and reset pulses generated at the same time difference by a unit pulse.
CONSTITUTION: The pulse width modulating circuit 1 is provided with output correcting means 9, 10 for inputting either one of a set pulse S4 and a reset pulse S6 and switching whether the inputted pulse is to be excessively delayed by a unit pulse based on the set value of pulse width setting data PWD for setting up the pulse width of an output pulse PWMOUT and the delayed pulse is to be applied to a latch means 8 or not. For instance, whether the set pulse S4 outputted from a delay means 4 is to be delayed by the unit pulse based on the set value of the data PWD and applied to the latch means 8 or not is switched and the delayed pulse is applied to the set input terminal of the means 8. Thus the time difference between the set pulse S4 and the reset pulse S6 generated at the same time difference is adjusted in each unit pulse.
More Like This:
| JP2007203603 | LIGHT EMITTING DEVICE, ELECTRONIC EQUIPMENT AND IMAGE PROCESSOR |
| JPH06135052 | OPTICAL PRINT HEAD |
| JP5100468 | Image forming device |
Inventors:
Hideki Yoshida
Daisuke Murakami
Daisuke Murakami
Application Number:
JP36154692A
Publication Date:
July 08, 2002
Filing Date:
December 29, 1992
Export Citation:
Assignee:
ソニー株式会社
International Classes:
B41J2/44; B41J2/47; H03H17/08; H03K5/13; H03K5/131; H03K7/08; H04B14/02; (IPC1-7): H03K5/13; B41J2/44; H03K7/08
Domestic Patent References:
| JP63287109A | ||||
| JP6043917A | ||||
| JP637608A | ||||
| JP6204826A | ||||
| JP621317A |
Attorney, Agent or Firm:
Keiki Tanabe