Title:
PULSE WIDTH MODULATION ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP3177637
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten maximum operation time and to maintain the accuracy of m bit by representing m bit PWM signal with n pieces of sub-PWM signals (n is a common divisor of m), independently and operating in parallel each sub PWM signal with a pulse modulation circuit and synthesizing operation results in a digital area.
SOLUTION: K pieces of high order and low order four bit sub-PWM signals, which represent k pieces of eight bit PWM signals are inputted. Output current pulses of each corresponding switch current source are overlapped on common buses 5 and 6. Reference charge count circuits 7 and 8 convert the overlapped current pulses into total charge quantity Q, that is in proportion to the sum total of pulses by capacity integration and outputs discretization value. Digital counter circuits 11 to 14 performs weight addition of each discretization value, and a digital counter 15 shifts the operation result of a PWM signal H by four bits in the direction of a MSB and adds it to the operation result of a PWM signal L. With this, the accuracy and speed of an operation are improved.
Inventors:
Mu Iwata
Makoto Nagata
Makoto Nagata
Application Number:
JP2280597A
Publication Date:
June 18, 2001
Filing Date:
February 05, 1997
Export Citation:
Assignee:
Hiroshima University Dean
International Classes:
G06G7/161; H03K9/08; H03M1/50; (IPC1-7): G06G7/161; H03M1/50
Domestic Patent References:
| JP61242422A | ||||
| JP7177038A | ||||
| JP63303516A | ||||
| JP3104420A | ||||
| JP5145420A | ||||
| JP5582846U |
Attorney, Agent or Firm:
Takehiko Suzue (5 outside)