To set an upper/lower limit value of duty cycle of pulse width modulation, without checking the value set in a register by a software without using a separate hardware, in a pulse width modulation signal generator circuit.

A pulse width modulation signal generator circuit 15, a setting means for setting a maximum/minimum value duty cycle, and a CPU12 having an instruction for transfer of a duty set value, are provided. When the duty cycle set value is transferred from the CPU12 in the case of this set value larger the maximum value set in the setting means, this maximum value is transferred, the duty cycle width of a pulse width modulation output is controlled to a value or less set in the setting means. Further, when the duty set value is transferred from the CPU12, in the case of its set value smaller than the minimum value set in the setting means, this minimum value is transferred, and the duty cycle width of the pulse width modulation output is controlled to a value or larger, set in the setting means.