PWM CONTROLLER FOR 3-LEVEL INVERTER

Japanese Patent JP3333883

B2

PROBLEM TO BE SOLVED: To provide a PWM controller for 3-level inverter in which the output voltage can be controlled continuously and faithfully to an instantaneous voltage command by regulating the width of voltage pulse on the reverse polarity side in the direction for shortening the zero voltage interval when any one of positive or negative output voltage pulse becomes shorter than a predetermined pulse width.
SOLUTION: A 3-level output voltage is generated through on/off control of switching elements in switching arms 7a,.... When any one of positive or negative output voltage pulse becomes shorter than a predetermined pulse width, distributors 30, 31, 33, 34 in a polarity decision distributor 3 regulate the width of voltage pulse on the reverse polarity side in the direction for shortening the zero voltage interval. More specifically, in a region where the width of output pulse is limited to a minimum pulse width during an interval when positive and negative voltage pulses are outputted through a zero voltage, the pulse width is regulated on the reverse polarity side to compensate for the power deficiency caused by the limitation. Consequently, the output voltage can be controlled faithfully to the instantaneous output voltage command thus realizing continuous control of output voltage.

Kiyoshi Nakata
Mutsuhiro Terunuma

JP18880295A

October 15, 2002

July 25, 1995

Click for automatic bibliography generation  

株式会社日立製作所

H02M7/48; H02M7/483; H03K7/08; (IPC1-7): H02M7/48; H03K7/08

JP698559A
JP549263A
JP5146160A
JP6311759A

Shigeru Sasaoka (1 person outside)

Previous Patent: TERMINAL SIDE COMMUNICATION EQUIPMENT, OPPOSITE COMMUNICATION EQUIPMENT FOR THE EQUIPMENT AND COMMUN...

Next Patent: 水中油型エマルジョンの製造方法