To provide a PWM(pulse width modulation) signal generating circuit from which a component to realize 0% to 100% duty ratio is eliminated.

The PWM signal generating circuit uses a count means 102 of n-bit configuration (n is a positive real number) that is operated for a count period of (2n-1) and provides an output of its count and a duty ratio control means that responds to a (2n-1) count end signal and generates a consecutive pulse train with a duty ratio corresponding to the count and optionally designated among output duty ratios from 0% to 100% corresponding to the count, allows the count means 102 to repetitively count the output of a clock selection section for the (2n-1) count period, and allows the duty ratio control means to select the duty ratio on the basis of the count that respectively corresponds to a duty ratio among the duty ratios from 0% to 100%, where a value to designate the corresponding duty ratio is selected from the counts.