Title:
PWM SIGNAL GENERATOR
Document Type and Number:
Japanese Patent JP3286962
Kind Code:
B2
Abstract:
PURPOSE: To calculate required data by an adder, which is a hardware, and generate a plurality of PWM signals at high frequencies.
CONSTITUTION: The on-width data of a PWM1 signals is fetched from an 8-bit latch 3 and then it is set on an 8-bit latch 9. The bits of a free-run counter 26 which counts up at a specified clock and those of the latch 9 are compared bit by a digital comparator 27. When all the corresponding bits of the two devices agree with each other, the digital comparator 27 outputs '1' and thereby the output of a TFF 29 which performs a toggle operation inverses. The off- width data of the PWM1 is fetched from a latch 5 and then the value fetched from the latch 5 and the value of the latch 9 are added by an adder 63 and the added value is set on the latch 9. Then, bit comparison is conducted in the same manner as shown above. When all the corresponding bits agree, the output of the TFF 29 inverses. The output of the TFF 29 can be inversed also by a trigger signal to a trigger terminal 402.
Inventors:
Junichi Into
Masaaki Moriya
Kazuto Watanabe
Masaaki Moriya
Kazuto Watanabe
Application Number:
JP18461494A
Publication Date:
May 27, 2002
Filing Date:
August 05, 1994
Export Citation:
Assignee:
Canon Inc
International Classes:
C04B41/52; H02M3/00; H02M7/48; H03K7/08; (IPC1-7): H02M7/48; H02M3/00
Domestic Patent References:
| JP4354206A | ||||
| JP5344779A | ||||
| JP622556A | ||||
| JP6153534A | ||||
| JP6165514A |
Attorney, Agent or Firm:
Hiroyuki Niwa (1 outside)