Title:
RADIATION NOISE PREVENTION PRINTED BOARD ARRANGING AND WIRING PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JP3109483
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a printed board arranging and wiring processing system for detecting EMC(electro-magnetic compatibility) of bypass capacitor addition at the time of an arranging and wiring processing, adding a bypass capacitor, preventing radiation noise generation and guaranteeing design quality.
SOLUTION: This system is provided with an electronic component power source pin extraction part 21 for extracting the power source pin of an electronic component, a wiring pattern extraction part 22 for extracting a wiring pattern from the power source pin to the via hole of a power source, a line length and line width inspection part 23 for inspecting the line length and line width of the extracted wiring pattern, a bypass capacitor addition possibility inspection part 24 for inspecting whether or not the addition of the bypass capacitor is possible, a wiring route change possibility inspection part 25 for inspecting whether or not a wiring route capable of the bypass capacitor addition is present in the case that the bypass capacitor can not be added in a present wiring route, a wiring route change execution part 26 for changing the wiring route, a bypass capacitor addition execution part 27 and an error display part 28 for performing error display in the case that the bypass capacitor can not be added even when the wiring route is changed.
Inventors:
Keiji Kondo
Application Number:
JP20256998A
Publication Date:
November 13, 2000
Filing Date:
July 17, 1998
Export Citation:
Assignee:
NEC
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP1097560A | ||||
| JP1049568A | ||||
| JP2128277A |
Attorney, Agent or Firm:
Asamichi Kato