PURPOSE: To prevent the generation of miswriting due to the reset of a write inhibited state of a RAM even when a CPU runs away and to surely protect data or the like stored in the RAM.

CONSTITUTION: This RAM write protecting circuit is provided with a RAM 18 for storing information, two FFs 14, 16 cascade-connected to two stages to control writing in the RAM 18, an address decoder 12 for determining the control conditions of these FFs 14, 16, the 1st gate circuit 13, the 2nd gate circuit 15, and an OR gate circuit 19 for outputting a signal obtained from the decoder 12 to the two FFS 14, 16 to reset the FFs 14, 16 and an '1' signal writing condition in the 1st FF 14 and that in the 2nd FF 16 are respectively differently set up so that the 3rd gate circuit 17 can not opened and data writing in the RAM 18 is inhibited until write control is continuously executed in respective conditions.