PURPOSE: To quicken a read as well as reduction in power consumption of emitter detection type memory cells, by lowering a read reference voltage only during read reference voltage only during read operation.

CONSTITUTION: Emitter detection type memory cells MC are connected to respective intersections between many word lines W and bit lines B. Read reference voltage VD applied to transistors connecting sense amplifier SA to bit lines B is temporarily lowered when a word line potential rises from a non-selection level up to a selection level. This reference voltage is developed by level-shifting the output of write amplifier WA. Thus, the reference voltage is lowered only during read operation to lower a read level, so that the power consumption would be reduced by increasing the load resistance of cells, the read time can be shortened.